mcuconf.h
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1 /*
2  ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
3  2011,2012 Giovanni Di Sirio.
4 
5  This file is part of ChibiOS/RT.
6 
7  ChibiOS/RT is free software; you can redistribute it and/or modify
8  it under the terms of the GNU General Public License as published by
9  the Free Software Foundation; either version 3 of the License, or
10  (at your option) any later version.
11 
12  ChibiOS/RT is distributed in the hope that it will be useful,
13  but WITHOUT ANY WARRANTY; without even the implied warranty of
14  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15  GNU General Public License for more details.
16 
17  You should have received a copy of the GNU General Public License
18  along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20 
21 /*
22  * STM32F4xx drivers configuration.
23  * The following settings override the default settings present in
24  * the various device driver implementation headers.
25  * Note that the settings for each driver only have effect if the whole
26  * driver is enabled in halconf.h.
27  *
28  * IRQ priorities:
29  * 15...0 Lowest...Highest.
30  *
31  * DMA priorities:
32  * 0...3 Lowest...Highest.
33  */
34 
35 #define STM32F4xx_MCUCONF
36 
37 /*
38  * HAL driver system settings.
39  */
40 #define STM32_NO_INIT FALSE
41 #define STM32_HSI_ENABLED TRUE
42 #define STM32_LSI_ENABLED TRUE
43 #define STM32_HSE_ENABLED TRUE
44 #define STM32_LSE_ENABLED FALSE
45 #define STM32_CLOCK48_REQUIRED TRUE
46 #define STM32_SW STM32_SW_PLL
47 #define STM32_PLLSRC STM32_PLLSRC_HSE
48 #define STM32_PLLM_VALUE 8
49 #define STM32_PLLN_VALUE 336
50 #define STM32_PLLP_VALUE 2
51 #define STM32_PLLQ_VALUE 7
52 #define STM32_HPRE STM32_HPRE_DIV1
53 #define STM32_PPRE1 STM32_PPRE1_DIV4
54 #define STM32_PPRE2 STM32_PPRE2_DIV2
55 #define STM32_RTCSEL STM32_RTCSEL_LSI
56 #define STM32_RTCPRE_VALUE 8
57 #define STM32_MCO1SEL STM32_MCO1SEL_HSI
58 #define STM32_MCO1PRE STM32_MCO1PRE_DIV1
59 #define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
60 #define STM32_MCO2PRE STM32_MCO2PRE_DIV5
61 #define STM32_I2SSRC STM32_I2SSRC_CKIN
62 #define STM32_PLLI2SN_VALUE 192
63 #define STM32_PLLI2SR_VALUE 5
64 #define STM32_PVD_ENABLE FALSE
65 #define STM32_PLS STM32_PLS_LEV0
66 #define STM32_BKPRAM_ENABLE FALSE
67 
68 /*
69  * ADC driver system settings.
70  */
71 #define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
72 #define STM32_ADC_USE_ADC1 FALSE
73 #define STM32_ADC_USE_ADC2 FALSE
74 #define STM32_ADC_USE_ADC3 FALSE
75 #define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
76 #define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
77 #define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
78 #define STM32_ADC_ADC1_DMA_PRIORITY 2
79 #define STM32_ADC_ADC2_DMA_PRIORITY 2
80 #define STM32_ADC_ADC3_DMA_PRIORITY 2
81 #define STM32_ADC_IRQ_PRIORITY 6
82 #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
83 #define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
84 #define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
85 
86 /*
87  * CAN driver system settings.
88  */
89 #define STM32_CAN_USE_CAN1 TRUE
90 #define STM32_CAN_USE_CAN2 FALSE
91 #define STM32_CAN_CAN1_IRQ_PRIORITY 11
92 #define STM32_CAN_CAN2_IRQ_PRIORITY 11
93 
94 /*
95  * EXT driver system settings.
96  */
97 #define STM32_EXT_EXTI0_IRQ_PRIORITY 6
98 #define STM32_EXT_EXTI1_IRQ_PRIORITY 6
99 #define STM32_EXT_EXTI2_IRQ_PRIORITY 6
100 #define STM32_EXT_EXTI3_IRQ_PRIORITY 6
101 #define STM32_EXT_EXTI4_IRQ_PRIORITY 6
102 #define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
103 #define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
104 #define STM32_EXT_EXTI16_IRQ_PRIORITY 6
105 #define STM32_EXT_EXTI17_IRQ_PRIORITY 15
106 #define STM32_EXT_EXTI18_IRQ_PRIORITY 6
107 #define STM32_EXT_EXTI19_IRQ_PRIORITY 6
108 #define STM32_EXT_EXTI20_IRQ_PRIORITY 6
109 #define STM32_EXT_EXTI21_IRQ_PRIORITY 15
110 #define STM32_EXT_EXTI22_IRQ_PRIORITY 15
111 
112 /*
113  * GPT driver system settings.
114  */
115 #define STM32_GPT_USE_TIM1 FALSE
116 #define STM32_GPT_USE_TIM2 FALSE
117 #define STM32_GPT_USE_TIM3 FALSE
118 #define STM32_GPT_USE_TIM4 FALSE
119 #define STM32_GPT_USE_TIM5 FALSE
120 #define STM32_GPT_USE_TIM8 FALSE
121 #define STM32_GPT_TIM1_IRQ_PRIORITY 7
122 #define STM32_GPT_TIM2_IRQ_PRIORITY 7
123 #define STM32_GPT_TIM3_IRQ_PRIORITY 7
124 #define STM32_GPT_TIM4_IRQ_PRIORITY 7
125 #define STM32_GPT_TIM5_IRQ_PRIORITY 7
126 #define STM32_GPT_TIM8_IRQ_PRIORITY 7
127 
128 /*
129  * I2C driver system settings.
130  */
131 #define STM32_I2C_USE_I2C1 FALSE
132 #define STM32_I2C_USE_I2C2 TRUE
133 #define STM32_I2C_USE_I2C3 FALSE
134 #define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
135 #define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
136 #define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
137 #define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
138 #define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
139 #define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
140 #define STM32_I2C_I2C1_IRQ_PRIORITY 5
141 #define STM32_I2C_I2C2_IRQ_PRIORITY 5
142 #define STM32_I2C_I2C3_IRQ_PRIORITY 5
143 #define STM32_I2C_I2C1_DMA_PRIORITY 3
144 #define STM32_I2C_I2C2_DMA_PRIORITY 3
145 #define STM32_I2C_I2C3_DMA_PRIORITY 3
146 #define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
147 #define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
148 #define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
149 
150 /*
151  * ICU driver system settings.
152  */
153 #define STM32_ICU_USE_TIM1 FALSE
154 #define STM32_ICU_USE_TIM2 FALSE
155 #define STM32_ICU_USE_TIM3 TRUE
156 #define STM32_ICU_USE_TIM4 FALSE
157 #define STM32_ICU_USE_TIM5 FALSE
158 #define STM32_ICU_USE_TIM8 FALSE
159 #define STM32_ICU_TIM1_IRQ_PRIORITY 7
160 #define STM32_ICU_TIM2_IRQ_PRIORITY 7
161 #define STM32_ICU_TIM3_IRQ_PRIORITY 7
162 #define STM32_ICU_TIM4_IRQ_PRIORITY 7
163 #define STM32_ICU_TIM5_IRQ_PRIORITY 7
164 #define STM32_ICU_TIM8_IRQ_PRIORITY 7
165 
166 /*
167  * PWM driver system settings.
168  */
169 #define STM32_PWM_USE_ADVANCED FALSE
170 #define STM32_PWM_USE_TIM1 FALSE
171 #define STM32_PWM_USE_TIM2 FALSE
172 #define STM32_PWM_USE_TIM3 FALSE
173 #define STM32_PWM_USE_TIM4 FALSE
174 #define STM32_PWM_USE_TIM5 FALSE
175 #define STM32_PWM_USE_TIM8 FALSE
176 #define STM32_PWM_TIM1_IRQ_PRIORITY 7
177 #define STM32_PWM_TIM2_IRQ_PRIORITY 7
178 #define STM32_PWM_TIM3_IRQ_PRIORITY 7
179 #define STM32_PWM_TIM4_IRQ_PRIORITY 7
180 #define STM32_PWM_TIM5_IRQ_PRIORITY 7
181 #define STM32_PWM_TIM8_IRQ_PRIORITY 7
182 
183 /*
184  * SERIAL driver system settings.
185  */
186 #define STM32_SERIAL_USE_USART1 FALSE
187 #define STM32_SERIAL_USE_USART2 FALSE
188 #define STM32_SERIAL_USE_USART3 FALSE
189 #define STM32_SERIAL_USE_UART4 FALSE
190 #define STM32_SERIAL_USE_UART5 FALSE
191 #define STM32_SERIAL_USE_USART6 FALSE
192 #define STM32_SERIAL_USART1_PRIORITY 12
193 #define STM32_SERIAL_USART2_PRIORITY 12
194 #define STM32_SERIAL_USART3_PRIORITY 12
195 #define STM32_SERIAL_UART4_PRIORITY 12
196 #define STM32_SERIAL_UART5_PRIORITY 12
197 #define STM32_SERIAL_USART6_PRIORITY 12
198 
199 /*
200  * SPI driver system settings.
201  */
202 #define STM32_SPI_USE_SPI1 FALSE
203 #define STM32_SPI_USE_SPI2 FALSE
204 #define STM32_SPI_USE_SPI3 FALSE
205 #define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
206 #define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
207 #define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
208 #define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
209 #define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
210 #define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
211 #define STM32_SPI_SPI1_DMA_PRIORITY 1
212 #define STM32_SPI_SPI2_DMA_PRIORITY 1
213 #define STM32_SPI_SPI3_DMA_PRIORITY 1
214 #define STM32_SPI_SPI1_IRQ_PRIORITY 10
215 #define STM32_SPI_SPI2_IRQ_PRIORITY 10
216 #define STM32_SPI_SPI3_IRQ_PRIORITY 10
217 #define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
218 
219 /*
220  * UART driver system settings.
221  */
222 #define STM32_UART_USE_USART1 FALSE
223 #define STM32_UART_USE_USART2 FALSE
224 #define STM32_UART_USE_USART3 TRUE
225 #define STM32_UART_USE_USART6 TRUE
226 #define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
227 #define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
228 #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
229 #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
230 #define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
231 #define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
232 #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
233 #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
234 #define STM32_UART_USART1_IRQ_PRIORITY 12
235 #define STM32_UART_USART2_IRQ_PRIORITY 12
236 #define STM32_UART_USART3_IRQ_PRIORITY 12
237 #define STM32_UART_USART6_IRQ_PRIORITY 12
238 #define STM32_UART_USART1_DMA_PRIORITY 0
239 #define STM32_UART_USART2_DMA_PRIORITY 0
240 #define STM32_UART_USART3_DMA_PRIORITY 0
241 #define STM32_UART_USART6_DMA_PRIORITY 0
242 #define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
243 
244 /*
245  * USB driver system settings.
246  */
247 #define STM32_USB_USE_OTG1 TRUE
248 #define STM32_USB_USE_OTG2 FALSE
249 #define STM32_USB_OTG1_IRQ_PRIORITY 14
250 #define STM32_USB_OTG2_IRQ_PRIORITY 14
251 #define STM32_USB_OTG1_RX_FIFO_SIZE 512
252 #define STM32_USB_OTG2_RX_FIFO_SIZE 1024
253 #define STM32_USB_OTG_THREAD_PRIO LOWPRIO
254 #define STM32_USB_OTG_THREAD_STACK_SIZE 128
255 #define STM32_USB_OTGFIFO_FILL_BASEPRI 0
256 
257