Macros
mcuconf.h File Reference

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Macros

#define STM32F4xx_MCUCONF
 
#define STM32_NO_INIT   FALSE
 
#define STM32_HSI_ENABLED   TRUE
 
#define STM32_LSI_ENABLED   TRUE
 
#define STM32_HSE_ENABLED   TRUE
 
#define STM32_LSE_ENABLED   FALSE
 
#define STM32_CLOCK48_REQUIRED   TRUE
 
#define STM32_SW   STM32_SW_PLL
 
#define STM32_PLLSRC   STM32_PLLSRC_HSE
 
#define STM32_PLLM_VALUE   8
 
#define STM32_PLLN_VALUE   336
 
#define STM32_PLLP_VALUE   2
 
#define STM32_PLLQ_VALUE   7
 
#define STM32_HPRE   STM32_HPRE_DIV1
 
#define STM32_PPRE1   STM32_PPRE1_DIV4
 
#define STM32_PPRE2   STM32_PPRE2_DIV2
 
#define STM32_RTCSEL   STM32_RTCSEL_LSI
 
#define STM32_RTCPRE_VALUE   8
 
#define STM32_MCO1SEL   STM32_MCO1SEL_HSI
 
#define STM32_MCO1PRE   STM32_MCO1PRE_DIV1
 
#define STM32_MCO2SEL   STM32_MCO2SEL_SYSCLK
 
#define STM32_MCO2PRE   STM32_MCO2PRE_DIV5
 
#define STM32_I2SSRC   STM32_I2SSRC_CKIN
 
#define STM32_PLLI2SN_VALUE   192
 
#define STM32_PLLI2SR_VALUE   5
 
#define STM32_PVD_ENABLE   FALSE
 
#define STM32_PLS   STM32_PLS_LEV0
 
#define STM32_BKPRAM_ENABLE   FALSE
 
#define STM32_ADC_ADCPRE   ADC_CCR_ADCPRE_DIV4
 
#define STM32_ADC_USE_ADC1   FALSE
 
#define STM32_ADC_USE_ADC2   FALSE
 
#define STM32_ADC_USE_ADC3   FALSE
 
#define STM32_ADC_ADC1_DMA_STREAM   STM32_DMA_STREAM_ID(2, 4)
 
#define STM32_ADC_ADC2_DMA_STREAM   STM32_DMA_STREAM_ID(2, 2)
 
#define STM32_ADC_ADC3_DMA_STREAM   STM32_DMA_STREAM_ID(2, 1)
 
#define STM32_ADC_ADC1_DMA_PRIORITY   2
 
#define STM32_ADC_ADC2_DMA_PRIORITY   2
 
#define STM32_ADC_ADC3_DMA_PRIORITY   2
 
#define STM32_ADC_IRQ_PRIORITY   6
 
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY   6
 
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY   6
 
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY   6
 
#define STM32_CAN_USE_CAN1   TRUE
 
#define STM32_CAN_USE_CAN2   FALSE
 
#define STM32_CAN_CAN1_IRQ_PRIORITY   11
 
#define STM32_CAN_CAN2_IRQ_PRIORITY   11
 
#define STM32_EXT_EXTI0_IRQ_PRIORITY   6
 
#define STM32_EXT_EXTI1_IRQ_PRIORITY   6
 
#define STM32_EXT_EXTI2_IRQ_PRIORITY   6
 
#define STM32_EXT_EXTI3_IRQ_PRIORITY   6
 
#define STM32_EXT_EXTI4_IRQ_PRIORITY   6
 
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY   6
 
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY   6
 
#define STM32_EXT_EXTI16_IRQ_PRIORITY   6
 
#define STM32_EXT_EXTI17_IRQ_PRIORITY   15
 
#define STM32_EXT_EXTI18_IRQ_PRIORITY   6
 
#define STM32_EXT_EXTI19_IRQ_PRIORITY   6
 
#define STM32_EXT_EXTI20_IRQ_PRIORITY   6
 
#define STM32_EXT_EXTI21_IRQ_PRIORITY   15
 
#define STM32_EXT_EXTI22_IRQ_PRIORITY   15
 
#define STM32_GPT_USE_TIM1   FALSE
 
#define STM32_GPT_USE_TIM2   FALSE
 
#define STM32_GPT_USE_TIM3   FALSE
 
#define STM32_GPT_USE_TIM4   FALSE
 
#define STM32_GPT_USE_TIM5   FALSE
 
#define STM32_GPT_USE_TIM8   FALSE
 
#define STM32_GPT_TIM1_IRQ_PRIORITY   7
 
#define STM32_GPT_TIM2_IRQ_PRIORITY   7
 
#define STM32_GPT_TIM3_IRQ_PRIORITY   7
 
#define STM32_GPT_TIM4_IRQ_PRIORITY   7
 
#define STM32_GPT_TIM5_IRQ_PRIORITY   7
 
#define STM32_GPT_TIM8_IRQ_PRIORITY   7
 
#define STM32_I2C_USE_I2C1   FALSE
 
#define STM32_I2C_USE_I2C2   TRUE
 
#define STM32_I2C_USE_I2C3   FALSE
 
#define STM32_I2C_I2C1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)
 
#define STM32_I2C_I2C1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)
 
#define STM32_I2C_I2C2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)
 
#define STM32_I2C_I2C2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)
 
#define STM32_I2C_I2C3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)
 
#define STM32_I2C_I2C3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)
 
#define STM32_I2C_I2C1_IRQ_PRIORITY   5
 
#define STM32_I2C_I2C2_IRQ_PRIORITY   5
 
#define STM32_I2C_I2C3_IRQ_PRIORITY   5
 
#define STM32_I2C_I2C1_DMA_PRIORITY   3
 
#define STM32_I2C_I2C2_DMA_PRIORITY   3
 
#define STM32_I2C_I2C3_DMA_PRIORITY   3
 
#define STM32_I2C_I2C1_DMA_ERROR_HOOK()    chSysHalt()
 
#define STM32_I2C_I2C2_DMA_ERROR_HOOK()    chSysHalt()
 
#define STM32_I2C_I2C3_DMA_ERROR_HOOK()    chSysHalt()
 
#define STM32_ICU_USE_TIM1   FALSE
 
#define STM32_ICU_USE_TIM2   FALSE
 
#define STM32_ICU_USE_TIM3   TRUE
 
#define STM32_ICU_USE_TIM4   FALSE
 
#define STM32_ICU_USE_TIM5   FALSE
 
#define STM32_ICU_USE_TIM8   FALSE
 
#define STM32_ICU_TIM1_IRQ_PRIORITY   7
 
#define STM32_ICU_TIM2_IRQ_PRIORITY   7
 
#define STM32_ICU_TIM3_IRQ_PRIORITY   7
 
#define STM32_ICU_TIM4_IRQ_PRIORITY   7
 
#define STM32_ICU_TIM5_IRQ_PRIORITY   7
 
#define STM32_ICU_TIM8_IRQ_PRIORITY   7
 
#define STM32_PWM_USE_ADVANCED   FALSE
 
#define STM32_PWM_USE_TIM1   FALSE
 
#define STM32_PWM_USE_TIM2   FALSE
 
#define STM32_PWM_USE_TIM3   FALSE
 
#define STM32_PWM_USE_TIM4   FALSE
 
#define STM32_PWM_USE_TIM5   FALSE
 
#define STM32_PWM_USE_TIM8   FALSE
 
#define STM32_PWM_TIM1_IRQ_PRIORITY   7
 
#define STM32_PWM_TIM2_IRQ_PRIORITY   7
 
#define STM32_PWM_TIM3_IRQ_PRIORITY   7
 
#define STM32_PWM_TIM4_IRQ_PRIORITY   7
 
#define STM32_PWM_TIM5_IRQ_PRIORITY   7
 
#define STM32_PWM_TIM8_IRQ_PRIORITY   7
 
#define STM32_SERIAL_USE_USART1   FALSE
 
#define STM32_SERIAL_USE_USART2   FALSE
 
#define STM32_SERIAL_USE_USART3   FALSE
 
#define STM32_SERIAL_USE_UART4   FALSE
 
#define STM32_SERIAL_USE_UART5   FALSE
 
#define STM32_SERIAL_USE_USART6   FALSE
 
#define STM32_SERIAL_USART1_PRIORITY   12
 
#define STM32_SERIAL_USART2_PRIORITY   12
 
#define STM32_SERIAL_USART3_PRIORITY   12
 
#define STM32_SERIAL_UART4_PRIORITY   12
 
#define STM32_SERIAL_UART5_PRIORITY   12
 
#define STM32_SERIAL_USART6_PRIORITY   12
 
#define STM32_SPI_USE_SPI1   FALSE
 
#define STM32_SPI_USE_SPI2   FALSE
 
#define STM32_SPI_USE_SPI3   FALSE
 
#define STM32_SPI_SPI1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 0)
 
#define STM32_SPI_SPI1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 3)
 
#define STM32_SPI_SPI2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)
 
#define STM32_SPI_SPI2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)
 
#define STM32_SPI_SPI3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)
 
#define STM32_SPI_SPI3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)
 
#define STM32_SPI_SPI1_DMA_PRIORITY   1
 
#define STM32_SPI_SPI2_DMA_PRIORITY   1
 
#define STM32_SPI_SPI3_DMA_PRIORITY   1
 
#define STM32_SPI_SPI1_IRQ_PRIORITY   10
 
#define STM32_SPI_SPI2_IRQ_PRIORITY   10
 
#define STM32_SPI_SPI3_IRQ_PRIORITY   10
 
#define STM32_SPI_DMA_ERROR_HOOK(spip)    chSysHalt()
 
#define STM32_UART_USE_USART1   FALSE
 
#define STM32_UART_USE_USART2   FALSE
 
#define STM32_UART_USE_USART3   TRUE
 
#define STM32_UART_USE_USART6   TRUE
 
#define STM32_UART_USART1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 5)
 
#define STM32_UART_USART1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 7)
 
#define STM32_UART_USART2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 5)
 
#define STM32_UART_USART2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)
 
#define STM32_UART_USART3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 1)
 
#define STM32_UART_USART3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)
 
#define STM32_UART_USART6_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 2)
 
#define STM32_UART_USART6_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 7)
 
#define STM32_UART_USART1_IRQ_PRIORITY   12
 
#define STM32_UART_USART2_IRQ_PRIORITY   12
 
#define STM32_UART_USART3_IRQ_PRIORITY   12
 
#define STM32_UART_USART6_IRQ_PRIORITY   12
 
#define STM32_UART_USART1_DMA_PRIORITY   0
 
#define STM32_UART_USART2_DMA_PRIORITY   0
 
#define STM32_UART_USART3_DMA_PRIORITY   0
 
#define STM32_UART_USART6_DMA_PRIORITY   0
 
#define STM32_UART_DMA_ERROR_HOOK(uartp)    chSysHalt()
 
#define STM32_USB_USE_OTG1   TRUE
 
#define STM32_USB_USE_OTG2   FALSE
 
#define STM32_USB_OTG1_IRQ_PRIORITY   14
 
#define STM32_USB_OTG2_IRQ_PRIORITY   14
 
#define STM32_USB_OTG1_RX_FIFO_SIZE   512
 
#define STM32_USB_OTG2_RX_FIFO_SIZE   1024
 
#define STM32_USB_OTG_THREAD_PRIO   LOWPRIO
 
#define STM32_USB_OTG_THREAD_STACK_SIZE   128
 
#define STM32_USB_OTGFIFO_FILL_BASEPRI   0
 

Macro Definition Documentation

#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY   6
#define STM32_ADC_ADC1_DMA_PRIORITY   2
#define STM32_ADC_ADC1_DMA_STREAM   STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY   6
#define STM32_ADC_ADC2_DMA_PRIORITY   2
#define STM32_ADC_ADC2_DMA_STREAM   STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY   6
#define STM32_ADC_ADC3_DMA_PRIORITY   2
#define STM32_ADC_ADC3_DMA_STREAM   STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADCPRE   ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_IRQ_PRIORITY   6
#define STM32_ADC_USE_ADC1   FALSE
#define STM32_ADC_USE_ADC2   FALSE
#define STM32_ADC_USE_ADC3   FALSE
#define STM32_BKPRAM_ENABLE   FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY   11
#define STM32_CAN_CAN2_IRQ_PRIORITY   11
#define STM32_CAN_USE_CAN1   TRUE
#define STM32_CAN_USE_CAN2   FALSE
#define STM32_CLOCK48_REQUIRED   TRUE
#define STM32_EXT_EXTI0_IRQ_PRIORITY   6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY   6
#define STM32_EXT_EXTI16_IRQ_PRIORITY   6
#define STM32_EXT_EXTI17_IRQ_PRIORITY   15
#define STM32_EXT_EXTI18_IRQ_PRIORITY   6
#define STM32_EXT_EXTI19_IRQ_PRIORITY   6
#define STM32_EXT_EXTI1_IRQ_PRIORITY   6
#define STM32_EXT_EXTI20_IRQ_PRIORITY   6
#define STM32_EXT_EXTI21_IRQ_PRIORITY   15
#define STM32_EXT_EXTI22_IRQ_PRIORITY   15
#define STM32_EXT_EXTI2_IRQ_PRIORITY   6
#define STM32_EXT_EXTI3_IRQ_PRIORITY   6
#define STM32_EXT_EXTI4_IRQ_PRIORITY   6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY   6
#define STM32_GPT_TIM1_IRQ_PRIORITY   7
#define STM32_GPT_TIM2_IRQ_PRIORITY   7
#define STM32_GPT_TIM3_IRQ_PRIORITY   7
#define STM32_GPT_TIM4_IRQ_PRIORITY   7
#define STM32_GPT_TIM5_IRQ_PRIORITY   7
#define STM32_GPT_TIM8_IRQ_PRIORITY   7
#define STM32_GPT_USE_TIM1   FALSE
#define STM32_GPT_USE_TIM2   FALSE
#define STM32_GPT_USE_TIM3   FALSE
#define STM32_GPT_USE_TIM4   FALSE
#define STM32_GPT_USE_TIM5   FALSE
#define STM32_GPT_USE_TIM8   FALSE
#define STM32_HPRE   STM32_HPRE_DIV1
#define STM32_HSE_ENABLED   TRUE
#define STM32_HSI_ENABLED   TRUE
#define STM32_I2C_I2C1_DMA_ERROR_HOOK ( )    chSysHalt()
#define STM32_I2C_I2C1_DMA_PRIORITY   3
#define STM32_I2C_I2C1_IRQ_PRIORITY   5
#define STM32_I2C_I2C1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_DMA_ERROR_HOOK ( )    chSysHalt()
#define STM32_I2C_I2C2_DMA_PRIORITY   3
#define STM32_I2C_I2C2_IRQ_PRIORITY   5
#define STM32_I2C_I2C2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_DMA_ERROR_HOOK ( )    chSysHalt()
#define STM32_I2C_I2C3_DMA_PRIORITY   3
#define STM32_I2C_I2C3_IRQ_PRIORITY   5
#define STM32_I2C_I2C3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_USE_I2C1   FALSE
#define STM32_I2C_USE_I2C2   TRUE
#define STM32_I2C_USE_I2C3   FALSE
#define STM32_I2SSRC   STM32_I2SSRC_CKIN
#define STM32_ICU_TIM1_IRQ_PRIORITY   7
#define STM32_ICU_TIM2_IRQ_PRIORITY   7
#define STM32_ICU_TIM3_IRQ_PRIORITY   7
#define STM32_ICU_TIM4_IRQ_PRIORITY   7
#define STM32_ICU_TIM5_IRQ_PRIORITY   7
#define STM32_ICU_TIM8_IRQ_PRIORITY   7
#define STM32_ICU_USE_TIM1   FALSE
#define STM32_ICU_USE_TIM2   FALSE
#define STM32_ICU_USE_TIM3   TRUE
#define STM32_ICU_USE_TIM4   FALSE
#define STM32_ICU_USE_TIM5   FALSE
#define STM32_ICU_USE_TIM8   FALSE
#define STM32_LSE_ENABLED   FALSE
#define STM32_LSI_ENABLED   TRUE
#define STM32_MCO1PRE   STM32_MCO1PRE_DIV1
#define STM32_MCO1SEL   STM32_MCO1SEL_HSI
#define STM32_MCO2PRE   STM32_MCO2PRE_DIV5
#define STM32_MCO2SEL   STM32_MCO2SEL_SYSCLK
#define STM32_NO_INIT   FALSE
#define STM32_PLLI2SN_VALUE   192
#define STM32_PLLI2SR_VALUE   5
#define STM32_PLLM_VALUE   8
#define STM32_PLLN_VALUE   336
#define STM32_PLLP_VALUE   2
#define STM32_PLLQ_VALUE   7
#define STM32_PLLSRC   STM32_PLLSRC_HSE
#define STM32_PLS   STM32_PLS_LEV0
#define STM32_PPRE1   STM32_PPRE1_DIV4
#define STM32_PPRE2   STM32_PPRE2_DIV2
#define STM32_PVD_ENABLE   FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY   7
#define STM32_PWM_TIM2_IRQ_PRIORITY   7
#define STM32_PWM_TIM3_IRQ_PRIORITY   7
#define STM32_PWM_TIM4_IRQ_PRIORITY   7
#define STM32_PWM_TIM5_IRQ_PRIORITY   7
#define STM32_PWM_TIM8_IRQ_PRIORITY   7
#define STM32_PWM_USE_ADVANCED   FALSE
#define STM32_PWM_USE_TIM1   FALSE
#define STM32_PWM_USE_TIM2   FALSE
#define STM32_PWM_USE_TIM3   FALSE
#define STM32_PWM_USE_TIM4   FALSE
#define STM32_PWM_USE_TIM5   FALSE
#define STM32_PWM_USE_TIM8   FALSE
#define STM32_RTCPRE_VALUE   8
#define STM32_RTCSEL   STM32_RTCSEL_LSI
#define STM32_SERIAL_UART4_PRIORITY   12
#define STM32_SERIAL_UART5_PRIORITY   12
#define STM32_SERIAL_USART1_PRIORITY   12
#define STM32_SERIAL_USART2_PRIORITY   12
#define STM32_SERIAL_USART3_PRIORITY   12
#define STM32_SERIAL_USART6_PRIORITY   12
#define STM32_SERIAL_USE_UART4   FALSE
#define STM32_SERIAL_USE_UART5   FALSE
#define STM32_SERIAL_USE_USART1   FALSE
#define STM32_SERIAL_USE_USART2   FALSE
#define STM32_SERIAL_USE_USART3   FALSE
#define STM32_SERIAL_USE_USART6   FALSE
#define STM32_SPI_DMA_ERROR_HOOK (   spip)    chSysHalt()
#define STM32_SPI_SPI1_DMA_PRIORITY   1
#define STM32_SPI_SPI1_IRQ_PRIORITY   10
#define STM32_SPI_SPI1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_DMA_PRIORITY   1
#define STM32_SPI_SPI2_IRQ_PRIORITY   10
#define STM32_SPI_SPI2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_DMA_PRIORITY   1
#define STM32_SPI_SPI3_IRQ_PRIORITY   10
#define STM32_SPI_SPI3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_USE_SPI1   FALSE
#define STM32_SPI_USE_SPI2   FALSE
#define STM32_SPI_USE_SPI3   FALSE
#define STM32_SW   STM32_SW_PLL
#define STM32_UART_DMA_ERROR_HOOK (   uartp)    chSysHalt()
#define STM32_UART_USART1_DMA_PRIORITY   0
#define STM32_UART_USART1_IRQ_PRIORITY   12
#define STM32_UART_USART1_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_DMA_PRIORITY   0
#define STM32_UART_USART2_IRQ_PRIORITY   12
#define STM32_UART_USART2_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_DMA_PRIORITY   0
#define STM32_UART_USART3_IRQ_PRIORITY   12
#define STM32_UART_USART3_RX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM   STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_USART6_DMA_PRIORITY   0
#define STM32_UART_USART6_IRQ_PRIORITY   12
#define STM32_UART_USART6_RX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM   STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USE_USART1   FALSE
#define STM32_UART_USE_USART2   FALSE
#define STM32_UART_USE_USART3   TRUE
#define STM32_UART_USE_USART6   TRUE
#define STM32_USB_OTG1_IRQ_PRIORITY   14
#define STM32_USB_OTG1_RX_FIFO_SIZE   512
#define STM32_USB_OTG2_IRQ_PRIORITY   14
#define STM32_USB_OTG2_RX_FIFO_SIZE   1024
#define STM32_USB_OTG_THREAD_PRIO   LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE   128
#define STM32_USB_OTGFIFO_FILL_BASEPRI   0
#define STM32_USB_USE_OTG1   TRUE
#define STM32_USB_USE_OTG2   FALSE
#define STM32F4xx_MCUCONF